This invention relates to the field of semiconductor manufacture and, more particularly, to a method and structure for a source local interconnect for a flash memory device.
Floating gate memory devices such as flash memories include an array of electrically-programmable and electrically-erasable memory cells. Typically, each memory cell comprises a single n-channel metal oxide semiconductor (NMOS) transistor including a floating gate interposed between a control (input) gate and a channel. A layer of high-quality tunnel oxide used as gate oxide separates the transistor channel and the floating gate, and an oxide-nitride-oxide (ONO) dielectric stack separates the floating gate from the control gate. The ONO stack typically comprises a layer of silicon nitride (Si3N4) interposed between underlying and overlying layers of silicon dioxide (SiO2). The underlying layer of SiO2 is typically grown on the first doped polycrystalline silicon (polysilicon) layer. The nitride layer is deposited over the underlying oxide layer, and the overlying oxide layer can be either grown or deposited on the nitride layer. The ONO layer maximizes the capacitive coupling between the floating gate and the control gate and minimizes the leakage of current.
To program a flash cell, the drain region and the control gate are raised to predetermined potentials above a potential applied to the source region. For example 12, volts are applied to the control gate, 0.0 volts are applied to the source, and 6.0 volts are applied to the drain. These voltages produce xe2x80x9chot electronsxe2x80x9d which are accelerated from the substrate across the gate oxide layer to the floating gate. Various schemes are used to erase a flash cell. For example, a high positive potential such as 12 volts is applied to the source region, the control gate is grounded, and the drain is allowed to float. More common erase bias"" conditions include: a xe2x80x9cnegative gate erasexe2x80x9d in which xe2x88x9210V is applied to the control gate (Vg), 6V is applied to the source (Vs), a potential of 0V is applied to the body (Vbody), and the drain is allowed to float (Vd); and a xe2x80x9cchannel erasexe2x80x9d which comprises a Vg of xe2x88x929V, a Vbody of 9V, and a Vs and Vd of 9V or floating. In each case these voltages are applied for a timed period, and the longer the period the more the cell becomes erased. A strong electric field develops between the floating gate and the source region, and negative charge is extracted from the floating gate across the tunnel oxide to the source region, for example by Fowler-Nordheim tunneling.
In a flash memory device, the sources associated with each transistor within a sector are tied together, typically through the use of conductive doping of the wafer to connect the sources of each transistor within a column. The columns within the sector are tied together using conductive plugs and a conductive line.
FIG. 1 depicts a cross section of a transistor and other structures of a conventional flash electrically-erasable programmable read-only memory (E2PROM) device. FIG. 1 depicts the following structures: semiconductor substrate assembly comprising a semiconductor wafer 10, transistor source 12 and drain 14 diffusion regions within semiconductor wafer 10, gate (tunnel) oxide 16, floating gates 18 typically comprising a first polysilicon layer, capacitor dielectric 20 typically comprising an oxide-nitride-oxide (ONO) stack, control gate (word line) 22 typically comprising a second polysilicon layer, a transistor stack capping layer 24 typically comprising silicon nitride (Si3N4) or tetraethyl orthosilicate (TEOS), oxide or nitride spacers 26, a planar dielectric layer 28 such as borophosphosilicate glass (BPSG), digit line plugs 30 connected to drain regions 14, and a conductive line 32 typically comprising aluminum which electrically couples each plug 30 within a row of transistors.
A goal of design engineers is to increase the density of the transistors to enable a decrease in the size of the semiconductor device. One way this can be accomplished is to decrease the size of the transistors. As a semiconductor die typically comprises transistors numbering in the millions, even a small decrease in the transistor size can result in a marked improvement in device density. One obstacle to decreasing the transistor size is that if the cross-sectional area of the source region 12 becomes too small the electrical resistance of the source diffusion region increases beyond a desirable level and the device may become unreliable. The undesirable increase in resistance is exacerbated by the relatively extreme length of the diffusion region which functions as a source region for all transistors within a column. Thus, to minimize the resistance the source region must be heavily doped with conductive atoms. One problem with providing a heavily doped source region is that the dopants tend to diffuse away from the source region, especially with high-temperature processing of subsequent manufacturing steps. The dopants can migrate into the channel region of the device thereby effectively decreasing the channel length interposed between the source and drain regions underneath the transistor stack. This decrease in channel length can produce problems known as xe2x80x9cshort channel effectsxe2x80x9d such as a transistor with a lowered threshold voltage, which itself can produce an unreliable device.
One method for allowing a decrease in transistor size by decreasing the source length which avoids short channel effects is to provide a source local interconnect (LI) 34 as depicted in FIG. 2. A source LI can comprise the use of a conductive interconnect which electrically couples each source in one column of transistors of a flash device with all other sources. The interconnect is typically formed from a single layer of patterned, conductively-doped polysilicon, a metal such as tungsten, or another conductive material lying between two adjacent columns of transistors. An LI of polysilicon and a method for forming the LI has been proposed by R. Lee in U.S. Pat. Nos. 5,149,665 and 5,270,240, each of which is assigned to Micron Technology, Inc. and incorporated herein by reference as if set forth in their entirety.
One concern with source local interconnects is to maintain an adequate isolation between the interconnect and the word lines (control gates) of each adjacent transistor to prevent shorting and to sustain the maximum voltage between the source and control gate of the flash device. For example, in program (write) mode, 12 volts can be applied to the control gate while 0 volts is applied to the source. While maintaining isolation is necessary, an attempt is made to keep the spacing between the LI and the word lines to a minimum so that the transistors, and thus the memory array, can be made as small as possible.
A method for forming a local interconnect for a semiconductor device, and an inventive structure resulting from the method, which reduces or eliminates the problems described above would be desirable.
The present invention provides a new method for forming a semiconductor device, and an inventive semiconductor device resulting from the method, which, among other advantages, allows for a more scaleable device than is found with flash memory devices having diffused sources. The inventive method and device further allows for minimal spacing between a local interconnect and adjacent transistor features.
In accordance with one embodiment of the invention a plurality of transistor stacks each having an associated source and drain region, a nitride capping layer, and nitride spacers formed along each stack is provided. During the etch of the transistor stacks the gate oxide is typically not completely removed from the source and drain regions and remains until later processing steps and protects the silicon wafer in the source/drain areas. A thin blanket nitride barrier layer is then formed over exposed surfaces. Next, a planarized blanket layer of borophosphosilicate glass (BPSG) is formed, and a blanket nitride layer is formed over the BPSG layer. A patterned photoresist layer is formed over the blanket nitride layer which has an opening therein located over the transistor sources. The nitride overlying the BPSG layer and the BPSG layer are etched using an anisotropic etch to keep sidewalls defined by the nitride and BPSG formed as nearly vertical as possible. During this etch the BPSG is only partially etched to leave a portion over the source region.
Next, the photoresist layer is removed and a blanket conformal nitride layer is formed and spacer etched to form nitride spacers along the BPSG sidewalls. After forming the spacers the BPSG remaining over the source regions is removed using a wet etch which is highly selective to nitride relative to BPSG such that very little of the nitride barrier layer is removed. As all exposed surfaces except for the BPSG to be removed are covered by the thin nitride barrier layer, the nitride spacers, or the nitride layer overlying the BPSG, a highly-selective wet etch can be used which has a high BPSG:nitride etch rate, rather than a dry etch which is much less selective between BPSG and nitride. A wet etch is avoided, for example to avoid etching the BPSG or damaging the tunnel oxide which is exposed with conventional processing. Subsequently, the thin nitride barrier layer and the remaining gate oxide over the source region is etched, and a conductive local interconnect layer is formed within the opening defined by the nitride to contact the source regions, for example using a damascene process. Finally, a contact and interconnect to the source local interconnect is provided.
In accordance with another embodiment of the invention, a plurality of transistor stacks each having an associated source and drain region, a nitride capping layer, and nitride spacers formed along each stack is provided. During the etch of the transistor stacks the gate oxide is typically not completely removed from the source and drain regions and remains until later processing steps and protects the silicon wafer in the source/drain areas. A thin blanket nitride barrier layer is then formed over exposed surfaces, and a BPSG layer is formed and planarized. While the BPSG is being planarized, it is possible to remove the thin nitride barrier layer from over the nitride capping layer, as well as part of the nitride capping layer itself. Next, a patterned photoresist layer is formed over the BPSG layer which leaves exposed a BPSG portion overlying the source regions. A wet etch is used to remove the exposed BPSG down to the thin nitride barrier layer, then the nitride barrier is etched to expose the source regions. A source local interconnect is formed, for example using a damascene process, then wafer processing continues.
An in-process device formed in accordance with one embodiment of the invention comprises at least two columns of transistors within a single sector of a memory device, with each transistor having a source region. A dielectric layer having an opening therein. defined by first and second dielectric sidewalls is formed over the-transistors, with one sidewall overlying each column of transistors. The device further comprises: first and second dielectric spacers, wherein each of the spacers covers one sidewall of the dielectric layer; and a conductive line partially formed between the two columns of transistors and partially formed in the opening in the dielectric layer between the first and second dielectric sidewalls, wherein the spacers separate the conductive line from physical contact with the dielectric layer, and wherein the conductive line electrically couples each source region of each transistor in each of the two columns of transistors.
Use of this process allows for a more easily controlled exposure of the source regions using a wet etch while protecting the gate oxide and other features from the etch. Thus the nitride spacers along the transistor stacks and along the BPSG layer can be formed to be very thin and the distance between the stacks themselves can be formed to be very narrow because of the controllable wet etch which is used to expose the source region and the thin nitride barrier layer used to protect various features from the wet etch.
Additional advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.